1. Field of the Invention
This invention relates to a high speed computing apparatus and, more particularly, to a concurrent vector processor architecture for signal and image processing.
2. Prior Art
Signal processing algorithms operate mainly with one-and two-dimensional data arrays. Typical applications include digital filtering, Fast Fourier Transform (FFT) and post-processing. These applications require an extremely high processing throughput to handle large size arrays. Traditionally, integrated signal processors have been designed either as general purpose processors or as special purpose processors. Each of these two approaches to processor architecture design requires tradeoffs to be made between high performance and generalpurpose capability. Only a few processor designs have attempted to provide high speed architectures which are also capable of efficiently performing a wide variety of signal processing algorithms.
Signal processing throughput requirements have been conventionally expressed in terms of a required number of multiplies and additions per second. General purpose signal processors attempt to meet these requirements by using extremely fast arithmetic units implemented with state of the art technology. A vector processor which utilizes arithmetic pipeline processing enables higher throughput to be achieved while employing conservative fabrication technology or to obtain a significant savings of silicon area. High speed data processing also requires the use of a very efficient data transfer mechanism which is capable of accessing multi-dimensional arrays.